What is 8051 architecture in microcontrollers


The 8051-Family (better: MCS-51) is a processor architecture from Intel. The original 8051 is now out of date, but there are hundreds of variants (derivatives) of it, some of which are state-of-the-art.

Characteristics of the original 8051:

  • Up to 64 kB of external data and program memory can be addressed
  • 128 bytes internal RAM (8052: 256 bytes)
  • 2 timers / counters (8052: 3 timers / counters)
  • 2 external interrupts
  • 4 8-bit I / O ports, two of them for access to external memory
  • Hardware UART

The original 8051 is a mask-programmed microcontroller; the ROM-less variant is called 8031. It requires at least 12 cycles for a command. Command and data memories are logically separated, even if they are addressed via a single multiplexed external bus - if external memories are used. Whether this is a Harvard architecture or a Von Neumann architecture is controversial (see discussion: 8051). In the standard circuit, no code can be executed as program code in the data memory. However, this can be achieved by interconnecting PSEN and RD via AND gates. This method is often used during program development, see BOOT-51.

A well-known representative of this family is the 80C535 from Infineon. Although it is now also out of date, it is still often used in school lessons. It is now called the C515 and will no longer be produced by Infineon as of July 2005. The only derivative from Infineon at the moment is the xc800 series (as of 2009).

More recent representatives of this family are z. B. the MicroConverter® from Analog Devices, the AT89 family from Atmel, the MSC12 family from Texas Instruments or the DS89C430 from Maxim (Dallas).

Modern 8051 derivatives offer, among other things, a higher clock frequency, I2C bus, DA converter and AD converter with a lower clock division. As a result, no longer 12, but only 6, 4 or even only one cycle are required to execute a command. An internal flash ROM as program memory eliminates the need to connect an external EPROM. In addition, some USB microcontrollers use an 8051 core, such as the EzUSB from Cypress, the TUSBxxxx series from Texas Instruments, or the AT89C5131A-M from Atmel.

The architecture is less suitable for C compilers because of the limited stack memory and the many necessary language extensions: push and pop commands are only available for the lower 256 bytes of RAM, which also contain the 4 banks of 8 registers. If you need a larger stack, you have to rely on the compiler emulating push and pop as slower XRAM accesses. (small <-> large memory model). The SFRs share 128 addresses with the upper part of the internal RAM. The SFRs are addressed directly, the upper 128 bytes of RAM indirectly. Both types of addressing are possible for the lower 128 byte RAM. Since this is an indirect access, the upper 128 bytes of RAM can also be used for the stack.

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