What is a data path in a processor

Functional units of a processor

General

A computer consists of various components that are structured differently depending on the computer architecture. In general, however, one can differentiate between the following components:

  • Processor core
  • Program and data memory
  • Peripheral units

One speaks of a Von-Neumann architecture when the program and data memory are in a common address space. Since a command that accesses the data memory requires a total of two memory accesses (fetch command itself from memory, access to data), there is a need for the command to require at least two clock cycles. This is also called the Von-Neumann bottleneck designated. Since the speed of processors has historically increased much faster than the speed of memory access, this bottleneck has become more and more relevant.

An improvement is the division into a program memory and a data memory, which can work independently of one another. this is the Harvard-Architecture. The program memory can be implemented as read-only memory.

Data path

The processor core consists of a data path and a control unit. The data path contains the registers and data memories, the arithmetic unit and the buses between the individual components.

register

In the case of registers, a distinction is made between registers for a special purpose or so-called registers for general use (GPR for engl. General Purpose Register).

Special purpose registers include:

  • accumulator - contains the results of the arithmetic unit
  • Stack pointer - is used as an address to the current value in the stack
  • Index register - a register which is generally used for addressing
  • Command counter - Address of the current (or mostly next) command
  • Command register - records the current command

Arithmetic unit

The arithmetic unit is used to manipulate data. There is also an arithmetic-logical unit (ALU for engl. Arithmetic Logic Unit) to disposal. This ALU supports various arithmetic operations. There is also a register with status flags that are set depending on the last result of the ALU (overflow, zero, ...).

Typical operations that an ALU can perform:

  • addition
  • subtraction
  • Two's complement
  • Logical AND, OR, XOR operation
  • Inversion
  • Shift operations

Typical status flags are:

  • transfer (C. for engl. Carry): If a carry occurs during an operation, the carry bit is stored in this flag
  • Overflow (V. for engl. oVerflow): Represents the number range exceeded for two's complement operands
  • zero (Z for engl. zero): This flag is set when the result is 0
  • negative (N for engl. Negatives): In the two's complement representation, the MSB represents the sign (0: positive, 1: negative)

Data storage

The data memory is usually designed in such a way that read or write access can be carried out during one cycle. To do this, the processor creates an address and initiates read or write access.

buses

The registers and functional units are interconnected via buses. A bus can either be implemented as a point-to-point connection. Multiplexers serve as a switch between two different inputs. But there is also the implementation of buses that several participants can access using tri-state output drivers.

Control unit

The control unit controls the process in the data path. A Von Neumann cycle is typically assumed to process a command. Depending on the processor architecture, the 5 sub-steps can be combined or a sub-step can be extended to several cycles.

Fetch Instruction (1)

The command currently addressed by the command counter is loaded from the command memory into the command register. The command counter is incremented to point to the next command.

Decode (2)

The command is evaluated by the instruction decoder. The corresponding control signals for the data path are set.

Fetch Operands (3)

The operands for the calculation are fetched from the registers or from the memory.

Execute (4)

The operation is carried out by the arithmetic unit. If the current command is a jump command, the command counter is loaded with the jump address.

Write Back (5)

The results are written back to the registers or memory (if necessary).

The individual sub-steps can be parallelized by pipelining. To do this, it is necessary to implement the individual parts in the data path independently.

realization

The control unit can be implemented in two different ways:

  • Hardwired: The logic for the individual commands is implemented in the design using concrete logic
  • Microcode: The control unit is itself a small processor that has stored a so-called microcode for each command that is executed.

The implementation using microcode is very flexible and it is possible to change the microcoding at a later date on processors that have already been delivered. The disadvantage is the slow process compared to the hardwired logic.